On which Pin(or combinationof it) Flash magic generate 3 reset pulese for 89LPC9xx (ISP micro).
As per MCB900 sch , it is generated from combinatio of DTR, RTS & TXD??
Can any body send timing diagrma of DTR,RTS & TXD signal at the start of programming of 89LPC9xx (ISP series) micros
DTR controls RST, but through logic gates, not directly as per the MCB900 schematic diagram.
The timing diagram for ISP entry can be found in the user manual for the LPC900 family from NXP.
Andy