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Messages - krunalrao

#1
ARM Cortex / Re: LPC1833 external SPI flash bootloader
August 19, 2021, 05:40:13 AM
I am very much aware that sample code is not a plug-and-play type.  I believe providing any information on the sample code will be okay for you. In the sample code, in the comment below lines are mentioned.

erasing, programming and verifying of SPIFI flash S25FL129P on
// Hitex LPC1800/LPC4300 evaluation board
// Adapted from code in NXP SPIFI Read/Write example
// see: http://sw.lpcware.com/?p=lpc18xx.git&a=tree
// $Id: FlashPrg.c 3895 2015-05-14 13:06:10Z andy $

I am not able to log in to this mentioned website. Do you have an NXP link for the same?

I assume that this andy is you only. S? now below is my main concern.

How can I find the exact RAM location to store the bootloader code.

I have tried the below code of descriptor, that does not work.

  0x80000000,                                  // programmable memory start address
  0x801FFFFF,                                  // programmable memory end address
  0x10000500,                                  // ram start address (for bootloader storage)
  0x10001FFF,                                  // ram end address (for bootloader storage)
  0x1000,                                     // programmable sector size in bytes
  0xFF,                                        // programmable memory erased value
  256,                                         // number of bytes to program at once
  115200,                                      // communication baudrate
  DESCRIPTOR_BOOTSTRAP_CORTEXUART,             // use ISP to download this bootloader
  115200,                                       // baudrate to use for downloading bootloader
  0,                                           // ram address for commmand mailbox (0 = not used)
  0,                                           // ram address for response mailbox (0 = not used)
  0,                 

To clear more, I am not asking something that I need to develop. I am asking which is already there in the sample code.

Looking forward to some detailed explanation!!!

Thanks in advance!!

Rao
#2
ARM Cortex / Re: LPC1833 external SPI flash bootloader
August 17, 2021, 10:05:44 PM
I have mapped RAM Location with the LPC datasheet and the address is correct only. Really appreciate it, if you can simplify your answer.
#3
ARM Cortex / LPC1833 external SPI flash bootloader
August 17, 2021, 03:55:35 AM
I have tried the same example (\Flash Magic\Bootloaders\External Memory\LPCxpresso18S37) in my LPC1833 board with flash ROM MX25L3233FM2I by changing the descriptor file, but it does not work.

I am new to the LPC18xx controller. In an earlier post, I read that the bootloader code needs to be store in the RAM location not in flash.

How can I find the exact RAM location to store the bootloader code?

I have tried the below code of descriptor, that does not work.

DESCRIPTOR_HEADER,                           // must be DESCRIPTOR_HEADER
  DESCRIPTOR_VERSION,                          // must be DESCRIPTOR_VERSION
  BOOTLOADER_FUNC_BASIC,                       // bootloader functionality (ORing of BOOTLOADER_FUNC_xxx)
  VERSION,                                     // version number of bootloader
  0x80000000,                                  // programmable memory start address
  0x801FFFFF,                                  // programmable memory end address
  0x10000500,                                  // ram start address (for bootloader storage)
  0x10001FFF,                                  // ram end address (for bootloader storage)
  0x1000,                                     // programmable sector size in bytes
  0xFF,                                        // programmable memory erased value
  256,                                         // number of bytes to program at once
  115200,                                      // communication baudrate
  DESCRIPTOR_BOOTSTRAP_CORTEXUART,             // use ISP to download this bootloader
  115200,                                       // baudrate to use for downloading bootloader
  0,                                           // ram address for commmand mailbox (0 = not used)
  0,                                           // ram address for response mailbox (0 = not used)
  0,   

               
Could anyone please provide some details to design the bootloader code?