Suggestion for SOLUTION:
constraint: we have GND,VCC,RXD,TXD,ISP_ENABLE and Reset on our programming connector.
As we got no feedback by NXP yet and need to redesign the PCB shortly, we decided to work around the problem the following way:
We leave the internal reset as is, including the watchdog stuff - and accept periodic reset pulses.
We make the reset-ic's output signal a bit softer (1000 Ohm serial) from IC to ARM
As programming adapter, we use the FM suggested hardware with a slight modification.
The reset signal will not be tristate, but ordinary 0/1, so FM is capable of driving the reset hard to 1.
As long as the incoming DTR (-> becoming RESET) is a clear signal, this should work fine, and the watchdog should have to remain in its doghouse
constraint: we have GND,VCC,RXD,TXD,ISP_ENABLE and Reset on our programming connector.
As we got no feedback by NXP yet and need to redesign the PCB shortly, we decided to work around the problem the following way:
We leave the internal reset as is, including the watchdog stuff - and accept periodic reset pulses.
We make the reset-ic's output signal a bit softer (1000 Ohm serial) from IC to ARM
As programming adapter, we use the FM suggested hardware with a slight modification.
The reset signal will not be tristate, but ordinary 0/1, so FM is capable of driving the reset hard to 1.
As long as the incoming DTR (-> becoming RESET) is a clear signal, this should work fine, and the watchdog should have to remain in its doghouse