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Could you let us know the below information about spifi_drv_M3.lib?

1. In the flash magic example code, this lib is directly used for the support of spi flash, so, is the library created from .a (NXP) or it is created in KEIL by using source code?

2. Do you have any source code to create .lib?

3. We got the source code for this from NXP, but by building the project in KEIL, .lib size is different and that does not work?

Currently, we need to add the support of an flash of MXIC which is not supported by the old spifi lib, so we are working to add the support of the flash in spilib source ccode and by doing so, we need to create the customized bootloader for the flash MX25V16xx.
2
I have gone through both MX25L1633E and MX25R6435F but did not find any software-related difference. My customized bootloader code runs in MX25L1633E successfully but failed in MX25R6435F.

By debugging the code, I found that the operation failed from the initial stage Memory_init(). In our MCUxpresso code, we observed the same failure. Can it be the spifi_drv_M3.lib issue?

FYI, we are able to flash the image via JTAG in MX25R6435F.
3
It would be best to compare the datasheets of the two devices and look for differences. Andy
4
Thanks for your kind support.

With a correct RAM address mapping, my customized BL is working fine for the Winbond flash ROM.

Quick concern: If a flash ROM having almost the same features as the supported QSPI device for LPC1833, then would the same customized BL work for the similar featured flash ROM?

Or there is any specific change required in the sample code?
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ARM Cortex / Re: LPC1833 external SPI flash bootloader
« Last post by Andy Ayre on August 19, 2021, 08:53:24 am »
You don't find the RAM location, you choose the RAM location. You can put the bootloader at any location in RAM that you wish. The only requirement is that the start address in the descriptor matches your linker map file. The descriptor tells Flash Magic where in RAM to download the bootloader to and start execution from.

Andy
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ARM Cortex / Re: LPC1833 external SPI flash bootloader
« Last post by krunalrao on August 19, 2021, 05:40:13 am »
I am very much aware that sample code is not a plug-and-play type.  I believe providing any information on the sample code will be okay for you. In the sample code, in the comment below lines are mentioned.

erasing, programming and verifying of SPIFI flash S25FL129P on
// Hitex LPC1800/LPC4300 evaluation board
// Adapted from code in NXP SPIFI Read/Write example
// see: http://sw.lpcware.com/?p=lpc18xx.git&a=tree
// $Id: FlashPrg.c 3895 2015-05-14 13:06:10Z andy $

I am not able to log in to this mentioned website. Do you have an NXP link for the same?

I assume that this andy is you only. S? now below is my main concern.

How can I find the exact RAM location to store the bootloader code.

I have tried the below code of descriptor, that does not work.

  0x80000000,                                  // programmable memory start address
  0x801FFFFF,                                  // programmable memory end address
  0x10000500,                                  // ram start address (for bootloader storage)
  0x10001FFF,                                  // ram end address (for bootloader storage)
  0x1000,                                     // programmable sector size in bytes
  0xFF,                                        // programmable memory erased value
  256,                                         // number of bytes to program at once
  115200,                                      // communication baudrate
  DESCRIPTOR_BOOTSTRAP_CORTEXUART,             // use ISP to download this bootloader
  115200,                                       // baudrate to use for downloading bootloader
  0,                                           // ram address for commmand mailbox (0 = not used)
  0,                                           // ram address for response mailbox (0 = not used)
  0,                 

To clear more, I am not asking something that I need to develop. I am asking which is already there in the sample code.

Looking forward to some detailed explanation!!!

Thanks in advance!!

Rao
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ARM Cortex / Re: LPC1833 external SPI flash bootloader
« Last post by Andy Ayre on August 18, 2021, 09:14:32 am »
We provide examples for users to adapt. If you go down the route of adapting then we don't have your changes or your hardware so you will have to debug it yourself. The support for external flash is not plug-and-play because of all of the variables - it's a development task.

Andy
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ARM Cortex / Re: LPC1833 external SPI flash bootloader
« Last post by krunalrao on August 17, 2021, 10:05:44 pm »
I have mapped RAM Location with the LPC datasheet and the address is correct only. Really appreciate it, if you can simplify your answer.
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ARM Cortex / Re: LPC1833 external SPI flash bootloader
« Last post by Andy Ayre on August 17, 2021, 09:02:04 am »
The RAM location is the sixth entry in the descriptor. This is where the interrupt vectors need to start. Andy
10
ARM Cortex / LPC1833 external SPI flash bootloader
« Last post by krunalrao on August 17, 2021, 03:55:35 am »
I have tried the same example (\Flash Magic\Bootloaders\External Memory\LPCxpresso18S37) in my LPC1833 board with flash ROM MX25L3233FM2I by changing the descriptor file, but it does not work.

I am new to the LPC18xx controller. In an earlier post, I read that the bootloader code needs to be store in the RAM location not in flash.

How can I find the exact RAM location to store the bootloader code?

I have tried the below code of descriptor, that does not work.

DESCRIPTOR_HEADER,                           // must be DESCRIPTOR_HEADER
  DESCRIPTOR_VERSION,                          // must be DESCRIPTOR_VERSION
  BOOTLOADER_FUNC_BASIC,                       // bootloader functionality (ORing of BOOTLOADER_FUNC_xxx)
  VERSION,                                     // version number of bootloader
  0x80000000,                                  // programmable memory start address
  0x801FFFFF,                                  // programmable memory end address
  0x10000500,                                  // ram start address (for bootloader storage)
  0x10001FFF,                                  // ram end address (for bootloader storage)
  0x1000,                                     // programmable sector size in bytes
  0xFF,                                        // programmable memory erased value
  256,                                         // number of bytes to program at once
  115200,                                      // communication baudrate
  DESCRIPTOR_BOOTSTRAP_CORTEXUART,             // use ISP to download this bootloader
  115200,                                       // baudrate to use for downloading bootloader
  0,                                           // ram address for commmand mailbox (0 = not used)
  0,                                           // ram address for response mailbox (0 = not used)
  0,   

               
Could anyone please provide some details to design the bootloader code?
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