Hello.
Have just tried the P89V51RD2 on an existing design that uses the 'C51RD2 chip.
Previously the 'C51 was programmed using Flash Magic and the DTR / RTS lines to trigger ISP entry. However, now programming the 'V51, I find that the DTR line holds the processor permanently in reset so it cannot enter ISP mode.
When I cut the track on the application PCB that connects DTR to the watchdog trip input to reset the processor all I have to do is just plug in the power once I 'START' Flash Magic, and it all runs fine. Unfortunately this means a new board issue for production though.
Question is this - is there any reason why Flash Magic has to hold the DTR in the state that on the 'C51 would be permanently resetting the processor? Sureley I am not the only one being forced to change from C51 to V51 that would be very grateful for a bit of compatability here? Perhaps implement the same use of DTR and RTS for the V51 as was the case for the C51?
Any comments from those at ESA would be much appreciated!
Post Edited (06-07-06 09:12)