LPC932A1 ISP issue

[johnfulgor]

Good morning,
1)I'm trying to enter ISP mode through timed pulses on RESET pin, but without success. The pulses are generated by a pin of another P89LPC932 in push-pull mode, while the VCC of the micro to be programmed is switched by a P-MOS. Either the micros are powered at 5V, through a green led which lower the voltage to 3.3V. I'm sure the micro to be programmed works, since it goes on executing the code in normal way, ignoring the pulses. Ground pins of the micros  are connected, voltage levels seems ok.... What may be the reason of the failure? Can anyone show me the plot af a really working RESET signal?
2)I'm a bit confused about ISP and ICP. How can be a micro forced to ICP instead of ISP? And if this is done by the same pulses on the RESET pin, how can the micro know which of the two methods enter?

Thank You
John

[Je Gold]

1. LPC900 micro programming MUST have stable Vdd=3.3 .... using LED's may not be reliable.

Flashmagic documentation has a some examples of the 3pulses on reset hardware entry method.
Page 5 from this app note http://www.flashmagictool.com/assets/resources/ISPHardwareEntryAppNote.pdf

Also other app notes from the flash magic web site http://www.flashmagictool.com/resources.html

2.   ISP requires the micro to be programmed via the UART and a computer running flashmagic via serial port.

ICP requires the micro to be programmed by a synchronously clocked signals (like SPI or I2C), hence a serial port from a computer can not be directly , a ICP Bridge circuit is needed (usually the bridge circuit is another micro that receives serial UART flash magic commands and then sends synchronously clocked signals to the target micro to be programmed).

For hardware ISP entry  3pulses are required on the reset
For hardware ICP entry  7pulses are required on the reset

Here's a app note for an ICP bridge circuit
http://www.flashmagictool.com/assets/resources/ICPBridgeVddSwitch.pdf  using the MCB900 development kit for the ICP bridge circuit.
(read in conjunction for NXP application note AN10258_2.pdf)

Joe